Verification & Validation (V&V) System Engineer, Designer

Verification & Validation (V&V) System Engineer, Designer

Deep dives into component and subsystem designs to develop and define verification approaches, types, levels in a clearly defined RVCM (requirements verification compliance matrix)

Collaborating with diverse technical teams such as software, mechanical, modem, and compliance teams to validate expectations for system-level and network-level operations, from concept through execution

Integrating and performing verification of the end-to-end RF communications system. Meeting with customers internally and externally to select components

Defining plans for on-orbit payload verification or satellite testing, based on identified requirements

Analyzing and mitigating potential self-interference and other system interference issues

Interpreting test results, troubleshooting issues, performing root-cause analysis for any test failures

Documenting test results, test coverage, and other key performance indicators (KPI) metrics

5+ years of space vehicle, bus, RF payload, or optical payload integration and test or related industry experience

5+ years of experience developing space or communication system test requirements, plans, and procedures for system design verification and validation.

5+ years of space system, bus, or payload engineering or related industry experience

5+ years of experience in space vehicle design and/or verification with launched products

4+ years of experience in the use of standard electronic lab test equipment (i.e. network analyzers, oscilloscopes, spectrum analyzers, function generators, multimeters, etc.)

4+ years of experience developing code in C, C++, Python, Docker, and Rust on Linux platform and experience with industry standard coding practices

Experience with testing satellite communications payloads, optical communications payload, spacecraft bus and constituent subsystems, or space vehicle level.