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About the role
Development and verification of C++/SystemC/TLM models for different SoC components Integration of new and existing models into subsystem and full Virtual Platform Software development and porting (Linux/Android) on Virtual Platform Regular interaction with stake holders to understand and address any issues Mandatory Requirements Degree (Masters/Bachelor or equivalent) in Electronics/Computer/Electrical Engineering Good knowledge of C, C++, SystemC and TLM Good Knowledge of computer architecture Knowledge of at least one scripting language (Python/tcl/perl) Basic knowledge of at least one on-chip communication protocol Excellent problem solving and analytical skills Strong communication and teamwork skills Desired Requirements 3+ years of experience in the area of Virtual Prototyping Verilog/SV/UVM Knowledge Knowledge of bus protocols such as AXI/AHB/APB/ACE Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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