Layout Animator

As a Memory Compiler Layout Developer, you will be responsible for the layout development and verification of memory compiler components. Your key responsibilities will include: - Designing and developing memory blocks such as Array, Row/Column decoder, sense amplifier, pre-charge, and control blocks for SRAM. - Performing layout verification tasks like LVS/DRC/Latchup, quality checks, and documentation. - Ensuring on-time delivery of block-level layouts with acceptable quality. - Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and milestones in a multi-project environment. - Guiding junior team members in executing sub block-level layouts and reviewing their work. - Contributing to effective project management and communicating effectively with engineering teams in India and Korea to ensure project success. In terms of qualifications and requirements, you should: - Be familiar with various levels of memory layouts, including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. - Have expertise in floor planning, power planning, and block area estimation for memory designs or compilers. - Be capable of performing leaf cell layout development and physical verification. - Possess adequate knowledge of schematics, interfacing with circuit designers and CAD, and process development teams. - Have a good understanding of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, and shielding. - Understand the impact of layout on circuit performance factors like speed, capacitance, power, and area. - Excel in problem-solving skills related to area, power, performance, and physical verification of custom layout. - Have experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL, and Verification tools like Mentor Calibre. - Demonstrate leadership qualities, multitasking abilities, and teamwork skills. - Be self-motivated, hardworking, goal-oriented, and possess excellent verbal and written communication skills. - Knowledge of Skill coding and layout automation is a plus. Please note that the company's additional details were not provided in the job description. As a Memory Compiler Layout Developer, you will be responsible for the layout development and verification of memory compiler components. Your key responsibilities will include: - Designing and developing memory blocks such as Array, Row/Column decoder, sense amplifier, pre-charge, and control blocks for SRAM. - Performing layout verification tasks like LVS/DRC/Latchup, quality checks, and documentation. - Ensuring on-time delivery of block-level layouts with acceptable quality. - Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and milestones in a multi-project environment. - Guiding junior team members in executing sub block-level layouts and reviewing their work. - Contributing to effective project management and communicating effectively with engineering teams in India and Korea to ensure project success. In terms of qualifications and requirements, you should: - Be familiar with various levels of memory layouts, including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. - Have expertise in floor planning, power planning, and block area estimation for memory designs or compilers. - Be capable of performing leaf cell layout development and physical verification. - Possess adequate knowledge of schematics, interfacing with circuit designers and CAD, and process development teams. - Have a good understanding of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, and shielding. - Understand the impact of layout on circuit performance factors like speed, capacitance, power, and area. - Excel in problem-solving skills related to area, power, performance, and physical verification of custom layout. - Have experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL, and Verification tools like Mentor Calibre. - Demonstrate leadership qualities, multitasking abilities, and teamwork skills. - Be self-motivated, hardworking, goal-oriented, and possess excellent verbal and written communication skills. - Knowledge of Skill coding and layout automation is a plus. Please note that the company's additional details were not provided in the job description.