Senior Physical Design Engineer

Hiring experienced DFT Engineers - Leading Global semiconductor Design Organization Experience: 4 to 12 Years Location: Hyderabad We are looking for an experienced Physical Design Engineer to work on advanced ASIC/SoC projects. The role involves end-to-end physical design activities, including floor planning, place & route, clock tree synthesis, timing closure, physical verification, and low-power implementation for cutting-edge semiconductor designs. Key Responsibilities: Perform end-to-end ASIC Physical Design including Floor planning, P&R, CTS, Routing, and Timing Closure. Execute Physical Verification (DRC, LVS, Antenna Checks) and support ECO implementation. Work on Low Power Design techniques such as Voltage Islands, Power Gating, and Substrate Bias. Perform STA, Signal Integrity (SI), IR Drop Analysis, and timing optimization. Collaborate with Front-End Design teams to resolve implementation challenges. Utilize Cadence/Synopsys Physical Design tools and TCL/Perl scripting for design automation. Eligibility Criteria: 4–12 years of experience in ASIC Physical Design. Hands-on experience with Floor planning, P&R, CTS, STA, Physical Verification, and Timing Closure. Experience working on 65nm or below technology nodes with low-power design methodologies. Proficiency in Cadence/Synopsys Physical Design tools, PrimeTime/PrimeTime-SI, and TCL/Perl scripting. Strong communication, debugging, and cross-functional collaboration skills. Interested candidates can share their resumes on [HIDDEN TEXT]