Chiplet RTL Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you ll discover the real differentiator is our culture. We push the limits of innovation to solve the world s most important challenges striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the CT Group, you will help bring to life cutting-edge designs. You will lead a front-end design and integration team, working closely with architecture, design verification, physical design, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience leading teams and developing RTL for SoC subsystems from architectural specification to silicon. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up PREFERRED EXPERIENCE: 12 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques Power Gating, Clock Gating Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 10 years experience in same. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.