DV Engineer

Strond Knowledge of System Verilog and UVM Proven Expertise in Architecting Complex Verification Environments using System Verilog and UVM Ability to quickly ramp-up on complex FPGA Interfaces and must have completed at least one full verification life cycle Strong Digital and verification Fundamentals Ability to Understand the specifications and must have experience developing BFMs/UVCs for industry standard protocols Ability to Analyze Functional and Code reports and experience with the verification closure Strong Written and verbal Communication Strong knowledge of Verilog/VHDL and must be able to read and understand the complex HDL Coding