GLS Verification Lead

Job Title: GLS Lead Engineers Experience: 7+yrs Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI /STA Engineers Job Responsibilitie sLead Gate Level Simulation (GLS) activities for SoC/IP verification programs .Develop and execute GLS test plans for functional and timing validation .Debug GLS failures related to timing, reset, initialization, X-propagation, and CDC issues .Work closely with RTL, DFT, STA, PD, and Verification teams to resolve issues .Analyze SDF annotation, setup/hold violations, and simulation mismatches .Automate GLS regression flows and improve verification efficiency .Support power-aware GLS and low-power verification activities .Drive closure of GLS signoff before tape-out .Required Skill sStrong experience in Gate Level Simulation (GLS ) and timing simulation s .Good understanding of Verilog/SystemVerilo g .Experience with VCS/Xcelium/Quest a simulators .Knowledge of SDF back-annotatio n, STA concept s, and CDC/RD C .Experience in debugging waveform issues using Verdi/DV E .Scripting knowledge in Perl/Python/Shell/TC L .Understanding of SoC architecture and ASIC design flow .Preferred Skill sExperience with low-power verification (UPF/CPF) .Exposure to DFT and scan validation .Knowledge of emulation/prototyping is an added advantage .Educatio nB.E/B.Tech/M.E/M.Tech in Electronics/ECE/EEE or related field . Interested can share CV to sharmila.b@acldigital.c om