Sr . Engineer

Job Description: You will be responsible for IP / sub-system level micro-architecture development and RTL coding. Prepare block/sub-system level timing constraints. Integrate IP/sub-system. Perform basic verification either in IP Verification environment or FPGA. Deep knowledge of mixed signal concepts Deep knowledge of RTL design fundamentals Deep knowledge of Verilog and System-Verilog Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence Floorplan efforts Code Verilog RTL for high performance designs Specify, design, and synthesize RTL blocks, optimize and floorplan them