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About the role
As a Member of Technical Staff at AMD, you will be responsible for leading and contributing to the verification of Network on Chip IPs and Subsystems. Your role will involve architecting, developing, and utilizing simulation and/or formal based verification environments at block and subsystem levels to ensure the functional correctness of Network-On-Chip (NOC) IPs, subsystems, and SOC designs. Key Responsibilities: - Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specifications - Collaborate with design engineers to debug tests and deliver functionally correct design blocks - Identify and implement coverage measures for stimulus quality improvements - Conduct coverage analysis to identify verification gaps and achieve closure on coverage metrics Preferred Experience: - Proficiency in developing UVM, OVM, VMM, and/or SystemVerilog, Verilog test benches - Familiarity with simulation tools/debug environments like Synopsys VCS, Cadence IES for testing block level/full chip SOCs and FPGAs - Strong understanding of different phases of ASIC and/or full custom chip development - Experience in block level NOC (Network on Chip) verification is a plus - Knowledge of verification protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is advantageous - Experience as a verification architect, establishing verification methodology, tools, and infrastructure for high-performance FPGAs, SOCs, and/or VLSI designs is beneficial - Familiarity with gate-level simulation, power verification, reset verification, contention checking, and abstraction techniques is a plus - Exposure to formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (VC-Formal, Magellan) is an advantage Qualification Required: - Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ years of experience Please note that AMD and its subsidiaries are equal opportunity, inclusive employers. All applicants will be considered without regard to various characteristics protected by law. AMD may utilize Artificial Intelligence in the selection process. For more details, refer to AMD's 'Responsible AI Policy' on their website. As a Member of Technical Staff at AMD, you will be responsible for leading and contributing to the verification of Network on Chip IPs and Subsystems. Your role will involve architecting, developing, and utilizing simulation and/or formal based verification environments at block and subsystem levels to ensure the functional correctness of Network-On-Chip (NOC) IPs, subsystems, and SOC designs. Key Responsibilities: - Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specifications - Collaborate with design engineers to debug tests and deliver functionally correct design blocks - Identify and implement coverage measures for stimulus quality improvements - Conduct coverage analysis to identify verification gaps and achieve closure on coverage metrics Preferred Experience: - Proficiency in developing UVM, OVM, VMM, and/or SystemVerilog, Verilog test benches - Familiarity with simulation tools/debug environments like Synopsys VCS, Cadence IES for testing block level/full chip SOCs and FPGAs - Strong understanding of different phases of ASIC and/or full custom chip development - Experience in block level NOC (Network on Chip) verification is a plus - Knowledge of verification protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is advantageous - Experience as a verification architect, establishing verification methodology, tools, and infrastructure for high-performance FPGAs, SOCs, and/or VLSI designs is beneficial - Familiarity with gate-level simulation, power verification, reset verification, contention checking, and abstraction techniques is a plus - Exposure to formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (VC-Formal, Magellan) is an advantage Qualification Required: - Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ years of experience Please note that AMD and its subsidiaries are equal opportunity, inclusive employers. All applicants will be considered without regard to various characteristics protected by law. AMD may utilize Artificial Intelligence in the selection process. For more details, refer to AMD's 'Responsible AI Policy' on their website.