Senior DFT Engineer

DFT architecture definition Understand SoC architecture and test requirements. Work very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage. Drive and optimize DFT architecture for high performance and efficiency: SCAN scan partition, compression, at-speed, IR and low power MBIST for memories JTAG boundary scan insertion Handle responsibilities pertaining to both block and top-level activities in Hierarchical Scan. Implementation Develop / Upgrade SCAN & MBIST Insertion flows Develop appropriate timing constraints for SCAN/MBIST modes and debug timing violations ATPG flow implementation catering to various fault models, test pattern generation SCAN , MBIST & BSCAN Pattern Simulation Solutions to test analog macros Post-Silicon bring-up/support Work with Evaluation/Test Engineering team to bring-up patterns on ATE Work on failure analysis as required Work with the Operation team on test cost and yield improvement Improve DFT methodology to be in sync with latest best practices and technology in the industry Work closely with physical design team throughout the development cycle. Should be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT. Requirements 4-8 years of industry experience in DFT domain. Must have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations. Must have hands-on experience working on post-silicon activities. Having working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred. Exceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe. Scripting skills in Perl/Python/TCL and a good command over HDLs. Candidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred. Prior experience of timing closure/physical design will be an added plus.