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About the role
Education : Bachelor/Masters engineering degree in Computer Science / Electrical / Micro-Electronics Responsibilities: Lead and develop Physical Design Methodologies emphasizing on best-in-class Methodologies for corporate wide digital flows using EDA tools from leading vendors like Cadence, Synopsys and Mentor Graphics Work with global CAD methodology development team to automate and integrate the above CAD flows for centralized deployment Provide strong technical expertise and consultations on place and route and rail analysis EDA flows to ADI s Business Units and ensure successful tapeouts of their products Desired Skills: Expertise in developing CAD Solutions in the areas of physical design using Cadence, Synopsys or Mentor Graphics EDA tool suite Experience in overall digital implementation flows (RTL to GDS II) and has a we'll-proven track record of being involved in successful multi-million gate SOC design tapeouts in nanometer technology Experience in low power design and implementation methodologies is desirable Experience in working on sub 10nm technologies is desirable Strong experience in automation of methodologies/solution using TCL, Python, PERL and Tk Debugging experience to debug vendor tool problems and interacting with designers to help tackle their problems Possess excellent interpersonal and communication skills to collaborate and influence design development groups across the globe
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