Analog Layout Engineer

As a fabless semiconductor design company headquartered in Bengaluru, Axiro Semiconductor is at the forefront of driving innovation in RF, wireless infrastructure, satellite communication (Satcom), and high-speed connectivity solutions. Backed by CG Power & Industrial Solutions Ltd., a part of the 120-year-old Murugappa Group, Axiro represents India's entry into the global semiconductor arena. With a world-class team spread across India, the US, and Europe, and expertise in RF, mmWave, GaN, and next-generation communication technologies, Axiro is shaping the future of global connectivity, computation, and communication. Key Responsibilities: - Execute full custom layout of analog/mixed-signal blocks such as ADCs, DACs, PLLs, LDOs, etc. - Collaborate with design engineers to optimize layout for performance, area, and reliability. - Perform layout verification, including DRC, LVS, and parasitic extraction. - Apply layout techniques to address issues like crosstalk, IR drop, and latch-up. - Support post-layout simulations and tapeout activities. - Maintain design documentation and participate in peer layout reviews. - Interface with packaging and assembly teams to ensure manufacturing compliance. - Work with the design and foundry team for wafer step plan and wafer matrix. Qualifications & Requirements: - Experience: 8-10 years of hands-on experience in RFIC/MMIC/analog/custom layout design using CMOS/SiGe processes. - Technical Expertise: Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. - Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus. - Process Knowledge: Familiarity with SiGe, BiCMOS, SOI, and BCD technologies is advantageous. - Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations. - Tools Proficiency: Experienced with Cadence and Calibre tools in a Linux environment. - Scripting skills in SKILL and Perl are desirable. - Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts. - Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus. - Soft Skills: Strong problem-solving and debugging skills, effective communication and teamwork, flexible, adaptable, and collaborative working style. As a fabless semiconductor design company headquartered in Bengaluru, Axiro Semiconductor is at the forefront of driving innovation in RF, wireless infrastructure, satellite communication (Satcom), and high-speed connectivity solutions. Backed by CG Power & Industrial Solutions Ltd., a part of the 120-year-old Murugappa Group, Axiro represents India's entry into the global semiconductor arena. With a world-class team spread across India, the US, and Europe, and expertise in RF, mmWave, GaN, and next-generation communication technologies, Axiro is shaping the future of global connectivity, computation, and communication. Key Responsibilities: - Execute full custom layout of analog/mixed-signal blocks such as ADCs, DACs, PLLs, LDOs, etc. - Collaborate with design engineers to optimize layout for performance, area, and reliability. - Perform layout verification, including DRC, LVS, and parasitic extraction. - Apply layout techniques to address issues like crosstalk, IR drop, and latch-up. - Support post-layout simulations and tapeout activities. - Maintain design documentation and participate in peer layout reviews. - Interface with packaging and assembly teams to ensure manufacturing compliance. - Work with the design and foundry team for wafer step plan and wafer matrix. Qualifications & Requirements: - Experience: 8-10 years of hands-on experience in RFIC/MMIC/analog/custom layout design using CMOS/SiGe processes. - Technical Expertise: Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. - Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus. - Process Knowledge: Familiarity with SiGe, BiCMOS, SOI, and BCD technologies is advantageous. - Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations. - Tools Proficiency: Experienced with Cadence and Calibre tools in a Linux environment. - Scripting skills in SKILL and Perl are desirable. - Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts. - Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus. - Soft Skills: Strong problem-solving and debugging skills, effective co