Firmware OR C Developer (Bengaluru)

Job Title: Senior C Programmer with Marvell chipset Experience Location: Bangalore, India Job Summary: We are seeking a highly skilled Senior Firmware Developer with solid expertise in C programming and hands-on experience with Marvell chipsets. The ideal candidate will be responsible for designing, developing, and optimizing firmware for embedded systems, ensuring high performance and reliability in our products. Key Responsibilities: - SDK Integration & Development: Integrate Marvell switch/routing SDKs (like CPSS) into Ciscos Network Operating Systems (such as IOS-XR or NX-OS). [1, 3] - Firmware/Driver Development: Write embedded C/C++ code for Linux device drivers, BSPs, and micro-controllers interacting directly with packet processors and ASICs. [1, 2] - Hardware Bring-Up & Debugging: Lead early-stage chip bring-up, write diagnostic tools, and perform hardware-software integration. [1, 2] - Performance Optimization: Tune the firmware and data-plane paths to minimize packet latency and maximize memory/throughput efficiency on constrained SOCs (e.g., ARM, MIPS, or RISC-V targets). [1, 2] - Protocol Programming: Program and manage Layer-2 and Layer-3 data planes, ensuring packet switching, routing, VLAN, and L2/L3 features flow flawlessly between the silicon and Cisco's NOS Job Title: Senior C Programmer with Marvell chipset Experience Location: Bangalore, India Job Summary: We are seeking a highly skilled Senior Firmware Developer with solid expertise in C programming and hands-on experience with Marvell chipsets. The ideal candidate will be responsible for designing, developing, and optimizing firmware for embedded systems, ensuring high performance and reliability in our products. Key Responsibilities: - SDK Integration & Development: Integrate Marvell switch/routing SDKs (like CPSS) into Ciscos Network Operating Systems (such as IOS-XR or NX-OS). [1, 3] - Firmware/Driver Development: Write embedded C/C++ code for Linux device drivers, BSPs, and micro-controllers interacting directly with packet processors and ASICs. [1, 2] - Hardware Bring-Up & Debugging: Lead early-stage chip bring-up, write diagnostic tools, and perform hardware-software integration. [1, 2] - Performance Optimization: Tune the firmware and data-plane paths to minimize packet latency and maximize memory/throughput efficiency on constrained SOCs (e.g., ARM, MIPS, or RISC-V targets). [1, 2] - Protocol Programming: Program and manage Layer-2 and Layer-3 data planes, ensuring packet switching, routing, VLAN, and L2/L3 features flow flawlessly between the silicon and Cisco's NOS