Source description
About the role
Job Description: Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:
- Perform CPU development and design integration for CPU subsystem.
- Micro-architecture and design of RISC based CPU.
- Explore latest technologies in processor for 5G application.
Minimum Qualifications
- Master Degree in Electrical Engineering, Computer Science or Computer Engineering. - At least 3 years of CPU related Architect/RTL/Verification/Implementation design experience - Knowledge and practical experience with common RISC CPU architecture. - Ability to bring design concept to successful silicon
Preferred Qualifications
-
PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS. - 5+ years of CPU related Architect/RTL/Verification/Implementation design experience - Familiarity with CPU architecture knowledge and micro-architecture knowledge - Familiarity with chip digital design flow, including RTL integration, simulation, STA, clock tree, or low power design - Familiarity with Symmetric Multi-threading (SMT), ARM/MIPS CPUs, or RISC-V. - Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture. - Cross-site working experience is a PLUS. - Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
-
#LI-DNI
More at Baidu USA
Related open roles
Senior RTL Design Engineer
San Francisco Bay Area · Onsite
CPU Design Architect / Principal Digital Design Engineer
San Francisco Bay Area · Onsite
Design Verification Engineer
San Francisco Bay Area · Onsite
SoC System Hardware Architect
San Francisco Bay Area · Onsite
SoC Memory Subsystem Architect
San Francisco Bay Area · Onsite
Low Power SoC Hardware Architect
San Francisco Bay Area · Onsite