Senior Design Verification Engineer

As a Principal Software Engineer in the Verification IP (VIP) team, you will play a crucial role in designing and developing high-quality VIP solutions for next-generation high-speed protocols. Your responsibilities will include: - Architecting, designing, and developing Verification IP (VIP) for industry-standard protocols with a focus on high quality. - Leading the development of VIP using SystemVerilog/UVM methodologies. - Defining verification strategies, test plans, and coverage models to ensure protocol compliance. - Driving protocol compliance, debugging, and performance optimization for VIP solutions. - Mentoring junior engineers and providing technical leadership to the team. - Working on customer issues, feature enhancements, and adoption of next-gen protocols. Your skills and experience should include: - Strong expertise in SystemVerilog and UVM-based verification. - Deep understanding of protocols such as PCIe, Ethernet, CXL, UCIe, and UALink. - Strong debugging skills at protocol and transaction levels. - Experience with coverage-driven verification, assertions (SVA), and scoreboarding. - Familiarity with simulation tools like Xcelium, VCS, and Questa. Preferred qualifications for this role: - Exposure to AI/ML-driven verification or Python-based automation. - Experience in performance analysis and system-level validation. - Knowledge of Formal Verification concepts would be a plus. - Prior experience in customer-facing or product engineering roles. In addition to the above, you will have the opportunity to work on cutting-edge high-speed protocols and next-gen standards, contribute to industry-leading VIP products, and be part of a collaborative environment with global semiconductor leaders. This role also offers strong career growth opportunities into technical leadership and architecture roles. As a Principal Software Engineer in the Verification IP (VIP) team, you will play a crucial role in designing and developing high-quality VIP solutions for next-generation high-speed protocols. Your responsibilities will include: - Architecting, designing, and developing Verification IP (VIP) for industry-standard protocols with a focus on high quality. - Leading the development of VIP using SystemVerilog/UVM methodologies. - Defining verification strategies, test plans, and coverage models to ensure protocol compliance. - Driving protocol compliance, debugging, and performance optimization for VIP solutions. - Mentoring junior engineers and providing technical leadership to the team. - Working on customer issues, feature enhancements, and adoption of next-gen protocols. Your skills and experience should include: - Strong expertise in SystemVerilog and UVM-based verification. - Deep understanding of protocols such as PCIe, Ethernet, CXL, UCIe, and UALink. - Strong debugging skills at protocol and transaction levels. - Experience with coverage-driven verification, assertions (SVA), and scoreboarding. - Familiarity with simulation tools like Xcelium, VCS, and Questa. Preferred qualifications for this role: - Exposure to AI/ML-driven verification or Python-based automation. - Experience in performance analysis and system-level validation. - Knowledge of Formal Verification concepts would be a plus. - Prior experience in customer-facing or product engineering roles. In addition to the above, you will have the opportunity to work on cutting-edge high-speed protocols and next-gen standards, contribute to industry-leading VIP products, and be part of a collaborative environment with global semiconductor leaders. This role also offers strong career growth opportunities into technical leadership and architecture roles.