Senior Principal Asic Verification Engineer

Role Overview: You will be responsible for Design Verification for interconnect IP and Tensilica Processor subsystems, with relevant experience in interconnect and subsystems strongly preferred. Your main tasks will include crafting verification plans, executing those plans to verify highly complex and configurable designs, collecting and closing coverage, working closely with cross-functional teams to identify coverage scope, and creating or working with UVM-based DV environment. Key Responsibilities: - Design Verification for interconnect IP and Tensilica Processor subsystems - Crafting verification plans and executing on those plans - Responsible for coverage collection and closure - Work closely with cross-functional teams to identify coverage scope - Responsible for creating or working with UVM based DV environment Qualifications: - 8+ years of design verification experience - BS (or higher) in EE/Computer Engineering Additional Details of the Company: Cadence is a pivotal leader in electronic design, with over 30 years of computational software expertise. The company's Intelligent System Design strategy delivers software, hardware, and IP to turn design concepts into reality. Cadence customers span various industries, including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health. Cadence offers an opportunity to work on cutting-edge technology in an environment that values creativity, innovation, and making an impact. The company's employee-friendly policies focus on physical and mental well-being, career development, learning opportunities, and celebrating success. The "One Cadence One Team" culture promotes collaboration, and employees get to work with a diverse team of passionate individuals dedicated to customer success. Role Overview: You will be responsible for Design Verification for interconnect IP and Tensilica Processor subsystems, with relevant experience in interconnect and subsystems strongly preferred. Your main tasks will include crafting verification plans, executing those plans to verify highly complex and configurable designs, collecting and closing coverage, working closely with cross-functional teams to identify coverage scope, and creating or working with UVM-based DV environment. Key Responsibilities: - Design Verification for interconnect IP and Tensilica Processor subsystems - Crafting verification plans and executing on those plans - Responsible for coverage collection and closure - Work closely with cross-functional teams to identify coverage scope - Responsible for creating or working with UVM based DV environment Qualifications: - 8+ years of design verification experience - BS (or higher) in EE/Computer Engineering Additional Details of the Company: Cadence is a pivotal leader in electronic design, with over 30 years of computational software expertise. The company's Intelligent System Design strategy delivers software, hardware, and IP to turn design concepts into reality. Cadence customers span various industries, including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health. Cadence offers an opportunity to work on cutting-edge technology in an environment that values creativity, innovation, and making an impact. The company's employee-friendly policies focus on physical and mental well-being, career development, learning opportunities, and celebrating success. The "One Cadence One Team" culture promotes collaboration, and employees get to work with a diverse team of passionate individuals dedicated to customer success.