DFT Lead

Looking for a DFT lead position with strong hands-on experience in DFT architecture design at RTL, Scan Synthesis and ATPG along with Post-silicon debug. Should have extensive understanding of the ATPG compression logic, JTAG. Understanding of MBIST and hands-on is value addition. Driving the DFT micro level architecture at RTL and come up with best methodology strategies which help on Area, Timing, Power Hands-on with scan insertion, DRC analysis, STA test mode Constraints development. Making Sure Equivalence checking with post-scan insertion. ATPG coverage analysis and improvements. Pattern simulations pre/post-timing. Co-working with SOC team on pattern porting and part of the post-silicon debug. Working on the advanced fault models and DFT methodology bring-up for new technology nodes. Mentoring and guiding the Juniors in the team. B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 8+ years of VLSI industry experience in block level or chip level DFT activities.