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About the role
Roles & Responsibilities: To train & lead, small team of 5 to 8 engineers. Design and verification of complex analog sub-blocks of PCIe, UCIe & DDR. Work with customers to understand sub-block requirement, performance specification & translate that into design. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Requirements: B.S. in Electrical Engineering (M.S. preferred) 5 to 8+ years of experience in practical analog/mixed signal design for analog IPs Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Relevant experience with PLL/SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experience leading a design team is highly preferred. Excellent communication skills are required
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