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About the role
Roles & Responsibilities: Run and debug SPICE-based and digital simulations for AMS/SoC IPs and subsystems.Understand analog and digital design intent, review simulation setups, and ensure correct test conditions.Analyze results using waveform/debug tools and identify root cause for functional mismatches.Work with designers to resolve analog/digital interface issues, model issues, and corner-case failures.Use simulation and waveform tools to speed up debug and improve verification turnaround time.Contribute to improving simulation workflows (run scripts, log parsing, automation, regression stability).Support mixed domain / co-simulation activities where applicable (e.g., SPICE + digital).Document verification findings, debug notes, and simulation methodology updates.Supervise, train, lead small team of 5 to 10 engineers Required Qualifications: 5 to 8 years of relevant experience in AMS verification / simulation / debug.Strong fundamentals of Analog and Digital concepts. Good working knowledge of Verilog / SystemVerilog concepts (test/control, connectivity, modeling).Hands-on experience with SPICE and digital simulation tools and debug environments.Ability to understand simulation environments and debug analog/digital design-related issues.Comfortable working in a collaborative team setup with clear communication. Tools & Environment: Analog/Custom: Virtuoso, PrimeSim, FineSim, HSPICEDigital Simulation & Debug: Xcelium, SimVisionWaveform/Analysis: WaveView (or equivalent)AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS) Roles & Responsibilities: Run and debug SPICE-based and digital simulations for AMS/SoC IPs and subsystems.Understand analog and digital design intent, review simulation setups, and ensure correct test conditions.Analyze results using waveform/debug tools and identify root cause for functional mismatches.Work with designers to resolve analog/digital interface issues, model issues, and corner-case failures.Use simulation and waveform tools to speed up debug and improve verification turnaround time.Contribute to improving simulation workflows (run scripts, log parsing, automation, regression stability).Support mixed domain / co-simulation activities where applicable (e.g., SPICE + digital).Document verification findings, debug notes, and simulation methodology updates.Supervise, train, lead small team of 5 to 10 engineers Required Qualifications: 5 to 8 years of relevant experience in AMS verification / simulation / debug.Strong fundamentals of Analog and Digital concepts. Good working knowledge of Verilog / SystemVerilog concepts (test/control, connectivity, modeling).Hands-on experience with SPICE and digital simulation tools and debug environments.Ability to understand simulation environments and debug analog/digital design-related issues.Comfortable working in a collaborative team setup with clear communication. Tools & Environment: Analog/Custom: Virtuoso, PrimeSim, FineSim, HSPICEDigital Simulation & Debug: Xcelium, SimVisionWaveform/Analysis: WaveView (or equivalent)AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS)