Source description
About the role
Experienced in crafting with Xilinx,Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog,VHDL and System Verilog) Minimum Qualifications . Educational Background: Requires 10-12 years of experience in FPGA designs with MTech / BTech in EE / EC domain Preferred Qualifications Hands on experience with FPGA vendor tools like Vivado,Quartus and Libero
More at Cisco
Related open roles
Failure Analysis Technical Leader
Bangalore
DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog
Bangalore
ASIC Analog Mixed Signal (AMS) Circuit Design Leader
Bangalore
SI/PI Technical Leader
Bangalore
ASIC DFT Engineering Technical Leader | MBIST, SCAN, ATPG
Bangalore
ASIC Emulation Engineer / Technical Leader
Bangalore