DFT Lead & Engineers

DFT Leads & Engineers Multiple Openings Experience: 418 Years Location: Bangalore / Hyderabad About the Role Cyient Semiconductors is looking for experienced Design for Test (DFT) Leads and Engineers to join our growing semiconductor team. This is an exciting opportunity to work on complex ASIC/SoC programs across advanced technology nodes, driving DFT implementation from architecture through silicon bring-up. Key Responsibilities & Required Skills: 418 years of hands-on experience in Design for Test (DFT) for complex SoC/ASIC designs.Lead/execute DFT architecture, planning, implementation, verification, and sign-off for complex SoCs and ASICs.Hands-on experience with Scan Insertion, Scan Compression, ATPG, MBIST/BIST, and Boundary Scan (JTAG/IEEE 1149.x).Strong expertise in Synopsys DFTMax/TetraMax and/or Cadence DFT tool suites.Own DFT simulation, test vector generation, fault coverage analysis, silicon bring-up, and production test.Experience with full-chip DFT implementation and ensuring high test coverage for successful silicon tape-outs, preferably on advanced technology nodes (14nm and below).Good understanding of SoC integration, synthesis, and Static Timing Analysis (STA).Strong scripting skills in Tcl, Perl, or Python to automate and optimize DFT flows.Ability to collaborate effectively with RTL, Physical Design, Verification, and other cross-functional teams throughout the development cycle.For Lead roles, mentor junior engineers, conduct technical reviews, drive project execution, and manage deliverables.Strong analytical, debugging, communication, and stakeholder management skills.Candidates who can join immediately or within a short notice period will be preferred. If you're looking to work on challenging ASIC/SoC programs with a global team, we'd love to connect with you. Interested Send your updated profile to ranjith.allam@cyientsemi.com Know someone who would be a great fit Please like, comment, and share this post within your network to help us reach the right talent. .