AMSV junior engineer

Position - AMSV junior engineer Roles and Responsibilities Understand AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS). Review specifications, develop testcases independently as per the VPLAN. Good debugging skills with respect to rtl, analog behavioural models and analog schematics Hands on technical experience in simulating testcases, debug SPICE and digital cosimulations for IPs, Subsystems and sub-blocks Understand analog and digital design intent, ensure correct test conditions, bug finding and reporting. Analyse results using waveform/debug tools and identify root cause for functional mismatch Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS and capture the functionality closely matching the actual circuit behaviour. Meet deadlines with high quality deliverables Actively upskill on project showing learning curve and being proactive technically Skills we are looking for: Strong understanding of of AMS verification methodologies including mixed signal cosimulation, assertion and checkers-based verification Proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms Good understanding of analog solver and simulator settings Proficient in Systemverilog, UVM and analog behavioral modelling languages (SV-RNM/Verilog-AMS/Verilog-A) Strong fundamentals of Analog and Digital concepts. Hands on experience with SPICE and digital simulation tools and debug environments Comfortable working in a collaborative team setup with clear communication Employ scripting languages (PERL, TCL, Python) for automation of tasks and efficiency in verification processes. Position - AMSV junior engineer Roles and Responsibilities Understand AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS). Review specifications, develop testcases independently as per the VPLAN. Good debugging skills with respect to rtl, analog behavioural models and analog schematics Hands on technical experience in simulating testcases, debug SPICE and digital cosimulations for IPs, Subsystems and sub-blocks Understand analog and digital design intent, ensure correct test conditions, bug finding and reporting. Analyse results using waveform/debug tools and identify root cause for functional mismatch Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS and capture the functionality closely matching the actual circuit behaviour. Meet deadlines with high quality deliverables Actively upskill on project showing learning curve and being proactive technically Skills we are looking for: Strong understanding of of AMS verification methodologies including mixed signal cosimulation, assertion and checkers-based verification Proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms Good understanding of analog solver and simulator settings Proficient in Systemverilog, UVM and analog behavioral modelling languages (SV-RNM/Verilog-AMS/Verilog-A) Strong fundamentals of Analog and Digital concepts. Hands on experience with SPICE and digital simulation tools and debug environments Comfortable working in a collaborative team setup with clear communication Employ scripting languages (PERL, TCL, Python) for automation of tasks and efficiency in verification processes. Bengaluru, Karnātaka, India Associate Position - AMSV junior engineer Roles and Responsibilities Understand AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS). Review specifications, develop testcases independently as per the VPLAN. Good debugging skills with respect to rtl, analog behavioural models and analog schematics Hands o... Position - AMSV junior engineer Roles and Responsibilities Understand AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS). Review specifications...