Design-for-Test Sen & Mid

Key Responsibilities DFT Implementation Develop and implement DFT architecture for complex SoCs and IPs. Perform Scan Insertion using Cadence Modus DFT . Define and implement: Full Scan Scan Compression Scan Chain Stitching Test Point Insertion Boundary Scan (JTAG) MBIST Integration LBIST (Preferred) ATPG & Fault Coverage Generate ATPG patterns using Cadence Modus. Analyze and improve fault coverage. Debug pattern generation issues and coverage gaps. Perform diagnostics and failure analysis. Synthesis & DFT Flow Execute synthesis using Cadence Genus . Work closely with RTL and Physical Design teams for DFT signoff. Support timing closure of DFT logic. Optimize DFT structures with minimal impact on PPA. Verification & Validation Perform DFT verification at RTL and gate level. Validate scan chains and test modes. Run simulations for: Scan Shift Capture Mode ATPG Pattern Validation MBIST Verification Silicon Bring-Up Support post-silicon validation and production testing. Analyze ATE test results and debug manufacturing failures. Collaborate with Product Engineering and Test Engineering teams. 3. DV: Key Responsibilities Verification Architecture & Strategy Architect and drive end-to-end verification strategies for complex NPU and RISC-V based SoCs. Define verification plans, test strategies, coverage metrics, and closure methodologies. Develop scalable and reusable verification environments using UVM. Leverage Formal Verification techniques to accelerate verification closure. NPU & AI Accelerator Verification Verify AI/ML accelerator architectures including: Neural Processing Units (NPU) Tensor Processing Engines Matrix Compute Units MAC Arrays Vector Processing Engines AI Data Movement Architectures Validate functionality, performance, and architecture compliance. RISC-V Verification Verify RISC-V processor subsystems and integration. Validate: Pipeline Functionality Cache Subsystems Interrupt Controllers MMU and Memory Subsystems Privileged Architecture Multi-Core Operation Develop processor verification scenarios and stress tests. UVM-Based Verification Develop and maintain: UVM Agents Drivers Monitors Scoreboards Reference Models Functional Coverage Models Create constrained-random and directed test scenarios. Drive verification closure using coverage-driven methodologies. Formal Verification Architect and execute Formal Verification solutions. Perform: Property Verification Assertion-Based Verification (SVA) Connectivity Verification Deadlock Analysis Security Checks Protocol Compliance Verification Formal Coverage Analysis Integrate Formal methodologies with simulation-based verification. SoC Verification Verify complex SoC subsystems involving: RISC-V CPUs NPUs NoC Fabric Memory Controllers DMA Engines High-Speed Interfaces Collaborate with RTL, Architecture, DFT, Firmware, and Software teams. Key Responsibilities DFT Implementation Develop and implement DFT architecture for complex SoCs and IPs. Perform Scan Insertion using Cadence Modus DFT . Define and implement: Full Scan Scan Compression Scan Chain Stitching Test Point Insertion Boundary Scan (JTAG) MBIST Integration LBIST (Preferred) ATPG & Fault Coverage Generate ATPG patterns using Cadence Modus. Analyze and improve fault coverage. Debug pattern generation issues and coverage gaps. Perform diagnostics and failure analysis. Synthesis & DFT Flow Execute synthesis using Cadence Genus . Work closely with RTL and Physical Design teams for DFT signoff. Support timing closure of DFT logic. Optimize DFT structures with minimal impact on PPA. Verification & Validation Perform DFT verification at RTL and gate level. Validate scan chains and test modes. Run simulations for: Scan Shift Capture Mode ATPG Pattern Validation MBIST Verification Silicon Bring-Up Support post-silicon validation and production testing. Analyze ATE test results and debug manufacturing failures. Collaborate with Product Engineering and Test Engineering teams. 3. DV: Key Responsibilities Verification Architecture & Strategy Architect and drive end-to-end verification strategies for complex NPU and RISC-V based SoCs. Define verification plans, test strategies, coverage metrics, and closure methodologies. Develop scalable and reusable verification environments using UVM. Leverage Formal Verification techniques to accelerate verification closure. NPU & AI Accelerator Verification Verify AI/ML accelerator architectures including: Neural Processing Units (NPU) Tensor Processing Engines Matrix Compute Units MAC Arrays Vector Processing Engines AI Data Movement Architectures Validate functionality, performance, and architecture compliance. RISC-V Verification Verify RISC-V processor subsystems and integration. Validate: Pipeline Functionality Cache Subsystems Interrupt Controllers MMU and Memory Subsystems Privileged Architecture Multi-Core Operation Develop processor verification scenarios and stress tests. UVM-Based Verification Develop and maintain: UVM Agents Drivers Monitors Scoreboards Reference Models Functional Coverage Models Create constrained-random and directed test scenarios. Drive verification closure using coverage-driven methodologies. Formal Verification Architect and execute Formal Verification solutions. Perform: Property Verification Assertion-Based Verification (SVA) Connectivity Verification Deadlock Analysis Security Checks Protocol Compliance Verification Formal Coverage Analysis Integrate Formal methodologies with simulation-based verification. SoC Verification Verify complex SoC subsystems involving: RISC-V CPUs NPUs NoC Fabric Memory Controllers DMA Engines High-Speed Interfaces Collaborate with RTL, Architecture, DFT, Firmware, and Software teams. ASIC Verification,UVM,SV,RISC V,Motor Control,AI Accelarator Bengaluru, Karnātaka, India Associate Key Responsibilities DFT Implementation Develop and implement DFT architecture for complex SoCs and IPs. Perform Scan Insertion using Cadence Modus DFT. Define and implement: Full Scan Scan Compression Scan Chain Stitching Test Point Insertion Boundary Scan (JTAG) MBIST Integration LBIST (Preferred)... Key Responsibilities DFT Implementation Develop and implement DFT architecture for complex SoCs and IPs. Perform Scan Insertion using Cadence Modus DF...