ASIC RTL Design Lead Engineer

We have a new requirement for ASIC RTL Design Lead Engineer for our client. This is a FT role. Experience: 7-15 Years Location: Noida Job Responsibilities: Strong ASIC RTL design (Verilog/SystemVerilog), CDC, Lint Experience in micro-architecture , integration, and debugging Exposure to synthesis, timing, and low-power design Team leadership and cross-functional collaboration skills Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering