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About the role
Role Description: We are a US-funded fabless chip design venture operating a lean execution hub in Andhra Pradesh (Vijayawada). We are seeking a Fractional Senior VLSI Architect (10-15 hours/week) to serve as a Technical Lead and Design Reviewer. Key Responsibilities: Conduct high-level architecture sign-offs and review RTL/verification code written by our junior engineering team (supported by AI-native EDA tools). Guide microarchitecture spec definitions for mature-node chips (e.g., RISC-V / IoT controllers). Participate in weekly 2-hour design review syncs and tapeout readiness evaluations. Engagement Terms: Retainer contract (USD or INR equivalent), fully remote, 1015 hours/week.
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