Elect Design and Analy Engr 4

Job Title: Elect Design and Analy Engr 4

Job Location: El Segundo, CA 90245 (Hybrid 1 day onsite per week)

Duration: 06 Months

Shift Time: 1st Shift 8:00 am – 4:30 pm

Position Responsibilities:

• Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.

• Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.

• Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.

• Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.

• Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.

• Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.

Required Skills:

• A Bachelor of Science degree in Engineering (specializing in Electrical, Mechanical, or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or equivalent non-US qualifications relevant to the job description

• Proven experience in ASIC/FPGA verification processes

• Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs

• Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions

• Demonstrated experience in implementing test plans effectively

• Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism

• Capability to design self-checking and reusable testbenches from the ground up

• Experience in developing Functional Coverage Models and achieving Code Coverage closure

• Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications

• Familiarity with waveform debug tools

• Revision Control Systems: svn, client's, git

• Proficient in Linux Environments

Preferred Skills:

• 10+ years of related work experience or an equivalent combination of education and experience

• Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience

• Experience with hardware-based integration and test of ASIC/FPGA designs

• Experience with hardware emulators, especially Palladium

• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)

• Proficient in scripting languages: Make, Perl, Python, etc.

• Familiarity with space-based design techniques and radiation mitigation

• Demonstrated history of 1st pass success with ASIC designs Pay rate: 66.82-83.65 USD per Hour Job type: Contract Division: eTeam Inc (US) Category: eTeam United States Reference: 26-61617