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About the role
About the Company (Industry & Sector) An advanced-technology scale-up at the crossroads of Quantum Computing, Artificial Intelligence and Semiconductor Engineering . The hardware division designs full-stack enterprise quantum computersspanning superconducting processors, cryogenic control electronics and RF instrumentationto unlock breakthroughs across life-sciences, finance, transportation and space. Role & ResponsibilitiesArchitect fully fault-tolerant, scalable quantum processors by crafting blueprints and error-correction strategies for next-generation devices, including patentable IP. Design, simulate and benchmark surface, LDPC and bosonic codes on noise-biased hardware; iterate solutions with cryo-control and fabrication teams. Build numerical tool-chains in Python/QuTiP/Qiskit to model error propagation, mitigation and gate-fidelity limits , delivering data-driven design insights. Prototype dynamical-decoupling and error-mitigation schemes that extend coherence and enable bias-preserving logical gates. Publish peer-reviewed papers, file patents and author internal DoE reports that steer roadmap and funding decisions. Champion rigorous peer reviews, mentor junior researchers and foster cross-functional knowledge-sharing. Skills & Qualifications Must-Have PhD/MS in Physics, Mathematics, Computer Science or allied field with a quantum focus. 3 + years designing quantum error-correction codes (surface, LDPC) and fault-tolerant architectures. Proficiency in Python, MATLAB and quantum-software stacks for large-scale simulations and data analysis. Hands-on experience with dynamical decoupling/error-mitigation techniques on experimental platforms. Robust record of peer-reviewed publications and successful research projects. Excellent problem-solving, communication and cooperative skills. Preferred Familiarity with noise-biased bosonic codes and autonomous error-correction methods. Experience writing DoE and experimental-improvement r .
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