Senior FPGA Professional

At GalaxEye Space, we are pioneering the next generation of Earth observation solutions with our cutting-edge satellite technology. As a fast-growing space-tech startup, our mission is to revolutionize the way we gather, process, and deliver geospatial intelligence. Join us to become a part of an agile, high-impact team working at the forefront of space innovation. Senior FPGA & Communications Engineer | 4+ Years Experience We are seeking an innovative and driven Senior FPGA & Communications Engineer with a strong foundation in developing HDL on FPGA. In this role, you will bridge the gap between hardware and software, architecting, designing, and optimizing advanced communication waveforms, transceiver architectures, and DSP algorithms for cutting-edge wireless applications. Key Responsibilities Knowing how to write precise Timing closure constraints Clock Domain Crossing (CDC): Mastery of safely moving data between asynchronous domains (ADC, DAC, DSP, and host bus) using asynchronous FIFOs and Gray coding to prevent metastability. Fixed-Point Arithmetic & Bit Growth: Knowing how to trace bit-width expansion across mixers and filters, applying proper rounding and saturation to prevent overflows without degrading the signal-to-noise ratio. Multi-Rate Filter Design: Expertise in designing and cascading Cascaded Integrator-Comb (CIC) and Finite Impulse Response (FIR) filters, including passband droop compensation. Hardened IP Integration: Experience instantiating and interfacing with the hardened PCIe Gen3 x4 or SERDES interfaces for high-throughput data streaming. Good to have Ability to structure HDL to infer FPGA pre-adders, and map NCO tables to EBRs while saving LRAMs for deep packet buffering. Digital Communication & RF Principles Understanding the impact of NCO phase truncation spurs, I/Q amplitude/phase imbalances, DC offsets, and digital aliasing on analog RF performance. Requirements Bachelor or Master degree in Electronics & Communication, Electrical Engineering, or a related scientific or engineering discipline. 4+ Years experience with solid record of having developed HDL. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.