Design Verification Engineer

Industry: Semiconductor / ASIC & SoC Design Verification — engineering team focused on verification of digital IP, blocks, and system-on-chip (SoC) integrations for embedded and telecom applications. This role is based in India and requires on-site presence to collaborate closely with RTL designers, architects, and integration teams. Primary Job Title: Design Verification Engineer (ASIC/SoC) Experience : 5 to 15 Years Only immediate joiners Role & Responsibilities Develop and execute formal verification plans for digital blocks and SoC integrations using SystemVerilog and UVM methodologies. Implement directed and constrainedrandom testbenches, stimulus generators, and assertions to validate RTL against specifications. Run simulations on industry simulators (VCS, Questa/Xcelium), analyze failures, debug RTL/testbench issues, and drive fixes with design teams. Measure and improve functional coverage; define coverage goals and close coverage holes using coverage-driven strategies. Automate regression flows and build verification infrastructure using scripting (Python/Tcl/Perl) and CI tools to speed up turnaround. Collaborate with architecture, synthesis, timing, and validation teams to support silicon bring-up, gate-level verification, and signoff activities. Skills & Qualifications Must-Have Proven experience with SystemVerilog for design verification Practical knowledge of UVM testbench methodology Experience with industry simulators (Synopsys VCS, Mentor Questa) Strong RTL verification skills (coverage-driven, constraint-random) Assertion-based verification (SVA) experience Scripting for automation and debug (Python, Tcl, or Perl) Preferred Experience with formal verification tools (e.g., JasperGold) Exposure to FPGA prototyping and emulation platforms (Palladium, Veloce) Low-power verification knowledge (UPF) and gate-level signoff experience Benefits & Culture Highlights Hands-on, fast-paced engineering environment with clear ownership and growth paths. Opportunities to work on full verification lifecycle—from IP to SoC and silicon bring-up. Collaborative on-site team culture emphasizing technical excellence, mentorship, and measurable impact. Location: Bangalore (On-site). GiGa-Ops Global Solutions is hiring experienced verification engineers who are passionate about building high-quality, production-grade silicon—if you thrive on deep technical challenges and delivering measurable verification outcomes, we encourage you to apply. Skills: formal verification,soc,design verification,ip