ASIC Design Verification Engineer

As a Verification Engineer at Google, you will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products. Your contributions will shape the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. You will work on the verification of Google's SOC offerings, collaborating with hardware architects and design engineers. Key Responsibilities: - Verify designs using verification techniques and methodologies. - Work cross-functionally to debug failures and ensure the functional correctness of the design. - Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, ensuring easy-to-use documentation. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 4 years of experience with SystemVerilog (SV) and Universal Verification Methodology (UVM). Preferred Qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. - Experience in low-power design verification. You will develop high-performance VIPs for protocols supported by our SOCs and collaborate on deploying the verification stack across a heterogeneous set of IPs. Additionally, you will build and verify a generalized class of system topology abstractions, developing associated methodologies and tools. Google values diversity and is committed to equal employment opportunity. We are an affirmative action employer, considering all qualified applicants regardless of background. If you require accommodation due to a disability or special need, please complete our Accommodations for Applicants form. As a Verification Engineer at Google, you will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products. Your contributions will shape the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. You will work on the verification of Google's SOC offerings, collaborating with hardware architects and design engineers. Key Responsibilities: - Verify designs using verification techniques and methodologies. - Work cross-functionally to debug failures and ensure the functional correctness of the design. - Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, ensuring easy-to-use documentation. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 4 years of experience with SystemVerilog (SV) and Universal Verification Methodology (UVM). Preferred Qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. - Experience in low-power design verification. You will develop high-performance VIPs for protocols supported by our SOCs and collaborate on deploying the verification stack across a heterogeneous set of IPs. Additionally, you will build and verify a generalized class of system topology abstractions, developing associated methodologies and tools. Google values diversity and is committed to equal employment opportunity. We are an affirmative action employer, considering all qualified applicants regardless of background. If you require accommodation due to a disability or special need, please complete our Accommodations for Applicants form.