Physical Design Lead, Google Cloud

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high-quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power, and area in mind. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities

Manage Physical design of complex System on a Chip (SoC) to Tape out while working with multiple team members.

Manage block and physical implementation and Quality of Results (QoR) (e.g., power, timing, area).

Collaborate with Register-Transfer Level (RTL) design, cross-site Physical Design, and CAD teams on micro architectural critical items for timing and power convergence

Qualifications

• Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 10 years of experience in ASIC design implementation flows.

• Experience in driving execution for low-power physical design implementation with industry standard synthesis and Static Timing Analysis (STA) tools.

• Experience in sign-off convergence including STA, electrical checks, and physical verification.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience in programming and scripting languages such as Python, TCL, or Perl.

• Experience in leading physical design teams working on digital designs that have taped-out and produced working silicon and delivering silicon.

• Experience in top-level floorplanning, block integration, static timing analysis, sign-off.