Senior Design Engineer, Edge AI, Google Cloud

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you’ll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical. You’ll be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities

Lead a complex ASIC subsystem.

Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.

Define high-performance hardware/software interfaces. Write micro architecture and design specifications.

Define efficient micro-architecture and block partitioning/interfaces and flows.

Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Qualifications

• Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.

• 5 years of experience with RTL development for ASIC subsystems using Verilog.

• Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.

• Experience with micro architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications

• Experience with scripting languages (e.g., Python or Perl).

• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.

• Knowledge of high performance and low power design techniques.

• Knowledge of FPGA, emulation platforms, and SoC architecture.

• Knowledge of assertion-based formal verification.