Senior Design For Testability Engineer, Silicon

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qualifications: Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging. Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD. Experience with STA constraints development and analysis for DFT modes and SDF simulations. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL). About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation. Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port (TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns. Participate in post-silicon activity like bring up, diagnostics and characterization. Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.