Analog Layout Design Engineer

Job Title: Analog/Layout Design Engineer Experience Required: 5 to 8 years Location: [Insert Location] Employment Type: Full-Time, Permanent Industry: Semiconductor, VLSI Engineering Department: Engineering Job Overview: We are looking for a skilled Analog/Layout Design Engineer with expertise in analog and custom digital block layout design. In this role, you will be responsible for creating high-quality layouts, performing rigorous layout verification, and ensuring timely delivery of block-level designs. You will lead and mentor junior team members while collaborating effectively with global engineering teams to meet project milestones and deliverables. Key Responsibilities: Design and develop critical analog and custom digital blocks for complex ICs. Perform layout verification tasks such as LVS/DRC, antenna checks, and quality checks to ensure design integrity. Ensure on-time delivery of block-level layouts with acceptable quality standards. Lead project planning, area/time estimation, scheduling, delegation, and execution across multiple projects. Mentor and guide junior engineers in the execution of sub-block layouts and review their work. Contribute to effective project management to meet project milestones. Communicate and coordinate with global engineering teams to ensure successful project execution. Required Qualifications & Skills: Experience: 5 to 8 years of hands-on experience in analog/custom layout design, specifically in advanced CMOS processes. Software Expertise: Proficiency in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS tools. Layout Experience: Direct experience designing layouts for critical blocks such as temperature sensors, PLL, ADC, DAC, LDO, bandgap references, charge pumps, current mirrors, comparators, and differential amplifiers. Fundamentals: Strong understanding of analog layout fundamentals such as matching, electro-migration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects (active and passive). Layout Impact: Ability to analyze and implement layout solutions considering speed, capacitance, power, and area effects. Physical Verification: Strong problem-solving skills in custom layout physical verification. Experience: Previous support in multiple tape-out cycles is an added advantage. Communication: Excellent verbal and written communication skills, with the ability to work effectively with cross-functional teams. Educational Requirements: Minimum Qualification: BE or MTech in Electronics/VLSI Engineering or a related field.