Senior Physical Design Engineer - Embedded System

As a Senior Physical Design Engineer at iSource Services for our prestigious client, you will be responsible for leading physical design activities with a focus on clock tree synthesis (CTS), clock clustering, and timing closure. Your role will involve performing interactive debug, delay balancing, and skew grouping to optimize designs, as well as closing complex interfaces with challenging clocking structures. You will also be expected to develop and maintain Tcl scripts to automate design flows, collaborate with RTL, verification, and cross-functional teams, and mentor junior engineers while providing technical guidance. Key Responsibilities: - Lead physical design activities with a focus on CTS, clock clustering, and timing closure - Perform interactive debug, delay balancing, and skew grouping to optimize designs - Close complex interfaces with challenging clocking structures - Develop and maintain Tcl scripts to automate design flows - Collaborate with RTL, verification, and cross-functional teams - Mentor junior engineers and provide technical guidance Qualifications Required: - Strong hands-on experience in Innovus (INVS) with CTS expertise - Experience in PCIe or other high-speed designs with complex timing - Strong Tcl scripting skills - Excellent problem-solving, analytical, and communication skills - Must be available for face-to-face discussions in Pune As a Senior Physical Design Engineer at iSource Services for our prestigious client, you will be responsible for leading physical design activities with a focus on clock tree synthesis (CTS), clock clustering, and timing closure. Your role will involve performing interactive debug, delay balancing, and skew grouping to optimize designs, as well as closing complex interfaces with challenging clocking structures. You will also be expected to develop and maintain Tcl scripts to automate design flows, collaborate with RTL, verification, and cross-functional teams, and mentor junior engineers while providing technical guidance. Key Responsibilities: - Lead physical design activities with a focus on CTS, clock clustering, and timing closure - Perform interactive debug, delay balancing, and skew grouping to optimize designs - Close complex interfaces with challenging clocking structures - Develop and maintain Tcl scripts to automate design flows - Collaborate with RTL, verification, and cross-functional teams - Mentor junior engineers and provide technical guidance Qualifications Required: - Strong hands-on experience in Innovus (INVS) with CTS expertise - Experience in PCIe or other high-speed designs with complex timing - Strong Tcl scripting skills - Excellent problem-solving, analytical, and communication skills - Must be available for face-to-face discussions in Pune