Senior/ Lead Verification Engineer

Build world class, cutting edge team, processes and verification architecture for high performance memory interface IP and associated testchips.Detailed Requirements :Lead a team of verification engineers to delivering high quality DDR and other memory interface PHY?s. Ensure skilling of the team both in terms of tools and protocol exposureEnsure growth and career development of teamManage project execution and deadlines and deliver high verified IP in a timely manner Build an agile verification environment with high levels of reuse and modularity Develop coverage and other necessary metrics to objectively define the quality of the verification effort Be a expert on memory interface protocols and drive verification well and beyond ?standard? practicesDrive channel and jitter modelling Drive firmware developmentMaintain sophisticated regression suites with varying levels of exhaustiveness Carefully map out a randomization strategyCreate verification collateral that will accompany the IPInteract with CTO and other technical leaders in the company to define verification roadmapDrive formal verification strategy and executionSupport IP through design phase as well as post-siliconUnderstand and optimally use available VIPPlan team composition and growthEductational qualifications :Bachelors degree in electronics/computer engineering/computer scienceMasters degree in electronics/computer engineering/computer science preferred Experience :10-15 yrsTechnical qualifications :Experience in leading verification for high performance memory interface IP like LPDDRx,DDRx, HMBx and/or GDDRx etc.. from scratch to post-silicon support (end-to-end verification cycle) and good understanding of associated protocols is very preferablePrior experience in leading high-performance verification teams and delivering on aggressive deadlines. Must be a hands-on technical leaderStrong skill and experience in system verilog and UVMStrong skill and experience in simulators (NCSim / VCS / ModelSim / Questa)Strong scripting skills in python, perl, C and C++Experience and exposure to standard industry protocols like AHB / AXI / ACE / ACE / APB / JtagExperience with using complex VIP, scoreboards, trackers, assertions etc.Experience with gate level simulation, power aware simulation and formal verification