Core EDA Engineers / Staff or Senior Staff Synthesis & Routing (C++)

You will be responsible for designing and developing core engines for logic synthesis, placement and routing, and timing and design optimization. This involves building high-performance systems using modern C++ with a focus on scalability and efficiency. Additionally, you will develop and refine algorithms for graph optimization, timing analysis, and physical design constraints. Your role will also include contributing to end-to-end design flows from RTL to implementation, debugging complex issues, and driving improvements in quality of results, runtime, and scalability. Collaboration with teams across FPGA architecture, silicon, and software tools will be essential. - Design and develop core engines for: - Logic synthesis - Placement and routing - Timing and design optimization - Build high-performance systems using modern C++, focusing on scalability and efficiency - Develop and refine algorithms for: - Graph optimization - Timing analysis - Physical design constraints - Contribute to end-to-end design flows from RTL to implementation - Debug complex issues across large, interdependent systems - Drive improvements in QoR (quality of results), runtime, and scalability - Collaborate with teams across FPGA architecture, silicon, and software tools Qualifications Required: - 6+ years of hands-on experience in EDA software development - Strong programming expertise in C++ (data structures, algorithms, performance optimization) - Proven experience contributing to core tool engines, including synthesis, placement & routing, and timing/optimization frameworks - Strong understanding of digital design concepts (RTL, netlists, timing), algorithm design, and optimization techniques - Experience working on large, complex codebases - Strong debugging and problem-solving skills If you have experience building or enhancing production-grade EDA tools, a strong background in graph algorithms, heuristics, or optimization techniques, familiarity with FPGA or ASIC physical design flows, and a passion for solving deep technical problems at scale, you are encouraged to apply. (Note: Any additional details about the company were not provided in the job description) You will be responsible for designing and developing core engines for logic synthesis, placement and routing, and timing and design optimization. This involves building high-performance systems using modern C++ with a focus on scalability and efficiency. Additionally, you will develop and refine algorithms for graph optimization, timing analysis, and physical design constraints. Your role will also include contributing to end-to-end design flows from RTL to implementation, debugging complex issues, and driving improvements in quality of results, runtime, and scalability. Collaboration with teams across FPGA architecture, silicon, and software tools will be essential. - Design and develop core engines for: - Logic synthesis - Placement and routing - Timing and design optimization - Build high-performance systems using modern C++, focusing on scalability and efficiency - Develop and refine algorithms for: - Graph optimization - Timing analysis - Physical design constraints - Contribute to end-to-end design flows from RTL to implementation - Debug complex issues across large, interdependent systems - Drive improvements in QoR (quality of results), runtime, and scalability - Collaborate with teams across FPGA architecture, silicon, and software tools Qualifications Required: - 6+ years of hands-on experience in EDA software development - Strong programming expertise in C++ (data structures, algorithms, performance optimization) - Proven experience contributing to core tool engines, including synthesis, placement & routing, and timing/optimization frameworks - Strong understanding of digital design concepts (RTL, netlists, timing), algorithm design, and optimization techniques - Experience working on large, complex codebases - Strong debugging and problem-solving skills If you have experience building or enhancing production-grade EDA tools, a strong background in graph algorithms, heuristics, or optimization techniques, familiarity with FPGA or ASIC physical design flows, and a passion for solving deep technical problems at scale, you are encouraged to apply. (Note: Any additional details about the company were not provided in the job description)