Padmi

Lead DFT Engineer

BangalorePosted 2 months ago
Electrical Electronics And Computer Hardware EngineeringSeniorFull Time
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Lead DFT Engineer Experience: 6–12 Years Location: Bengaluru About the Role We are looking for a highly skilled Lead DFT Engineer with strong hands-on expertise in Scan Insertion, MBIST, and ATPG to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own the DFT flow from architecture through silicon bring-up while collaborating closely with RTL, Physical Design, Verification, and Product Engineering teams. What You'll Do Drive end-to-end DFT implementation for complex SoCs and IPs. Own Scan Architecture, Scan Insertion, Scan Compression , and scan chain verification. Develop and integrate MBIST architecture for embedded memories and debug implementation issues. Generate, analyze, and optimize ATPG patterns for stuck-at, transition, and other structural fault models. Perform DFT verification using simulation and ensure coverage targets are achieved. Debug DFT issues across RTL, gate-level, and post-layout stages. Work closely with Physical Design teams to achieve DFT timing closure and successful implementation. Support silicon bring-up, production test, and yield improvement activities. What We're Looking For 6–12 years of hands-on experience in DFT implementation . Strong expertise in Scan Insertion, Scan Compression, MBIST, and ATPG . Hands-on experience with Siemens Tessent (Scan, MBIST, ATPG) or equivalent industry-standard DFT tools. Strong understanding of scan methodologies, fault models, JTAG/IEEE 1149.1, and DFT architectures. Experience with RTL integration, gate-level simulations, and DFT verification. Good understanding of synthesis and Physical Design constraints related to DFT implementation. Proficiency in Tcl, Perl, Python, or Shell scripting . Excellent debugging, analytical, and problem-solving skills. Preferred Qualifications Experience with advanced technology nodes ( 3nm/5nm/7nm/12nm ). Exposure to IJTAG (IEEE 1687), LBIST, boundary scan, and hierarchical DFT methodologies. Experience with full-chip DFT integration and silicon bring-up. Ability to mentor engineers and drive technical execution across complex projects.

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