Lead Static Timing Analysis (STA) Engineer

Lead Static Timing Analysis (STA) Engineer Location: Bengaluru, India Experience: 6–12 Years About the Role We are looking for a Lead STA Engineer to drive timing closure and signoff for complex SoCs across advanced process nodes. You will work closely with RTL, Synthesis, Physical Design, CTS, and Signoff teams to deliver high-performance, power-efficient silicon. What You'll Do Drive block and full-chip STA from synthesis to tape-out. Own timing closure for setup, hold, recovery/removal, clock gating, and asynchronous paths . Perform MMMC, OCV/AOCV/POCV, SI-aware STA , and Path-Based Analysis (PBA). Develop and validate SDC constraints , timing exceptions, and ECOs. Collaborate with Physical Design and CTS teams to resolve timing bottlenecks. Debug complex timing issues and ensure signoff-quality timing closure. Mentor junior engineers and lead timing closure activities. What We're Looking For 6–12 years of ASIC/SoC STA experience. Strong expertise in Synopsys PrimeTime , PrimeTime SI, and Cadence Tempus . Deep understanding of MMMC, STA Signoff, Timing ECO, CTS, SI, SDC, and OCV methodologies . Hands-on experience on advanced nodes ( 16nm/7nm/5nm/3nm ). Proficiency in TCL, Perl, or Python scripting. Strong understanding of digital design and Physical Design flow. Preferred Experience with Fusion Compiler, ICC2, Innovus, Design Compiler . Exposure to PCIe, DDR, CXL, Ethernet, USB , or other high-speed interfaces. Knowledge of EMIR and low-power (UPF/CPF) methodologies. Join us to build next-generation silicon by solving some of the industry's most challenging timing closure and signoff problems.