Senior Design Verification Engineer

Senior Design Verification Engineer Location: Bengaluru Experience: 5–12 Years About the Role Join a high-performance silicon engineering team building next-generation SoCs for AI, Data Center, Networking, and Compute platforms. You will own the verification of complex IPs and SoCs, developing robust UVM environments and driving functional verification to silicon success. What You'll Do Develop scalable SystemVerilog/UVM verification environments. Verify complex IPs/SoCs with focus on PCIe, DDR, HBM, and Ethernet protocols. Create constrained-random testbenches, assertions, scoreboards, and coverage models. Drive functional verification, regression, coverage closure, and debug. Collaborate with Architecture, RTL, and Design teams to ensure first-pass silicon success. What We're Looking For 5–12 years of hands-on IP/SoC Verification experience. Strong expertise in SystemVerilog, UVM, and SVA . Deep verification experience in one or more of PCIe, DDR, HBM, or Ethernet . Solid understanding of Computer Architecture and ARM-based SoC architecture . Strong debugging, scripting, and problem-solving skills. Preferred: AXI/AHB/APB/CHI, Python/Perl, VCS/Xcelium/Questa, Verdi, Formal or Emulation exposure.