Senior Staff Engineer

Senior Staff Engineer – Physical Design (STA) Location: Bengaluru, India Experience: 10–15 Years About the Role We are looking for a Senior Staff Engineer – Physical Design (STA) to lead timing signoff and closure for high-performance SoCs on advanced technology nodes. You will solve complex timing challenges, drive signoff methodology, and collaborate with cross-functional teams to deliver first-pass silicon. Key Responsibilities Own end-to-end Static Timing Analysis (STA) from synthesis to final signoff. Drive MCMM timing closure across functional, scan, and low-power modes. Analyze and resolve setup/hold, SI/Crosstalk, OCV/AOCV/POCV, CRPR , and clock-related timing violations. Develop and validate SDC constraints , timing exceptions, and clock definitions. Execute ECO timing closure through logic optimization, cell sizing, buffering, and useful skew techniques. Partner with RTL, Synthesis, Physical Design, CTS, DFT, and Signoff teams to achieve timing convergence. Contribute to STA methodology, automation, and best practices for advanced-node designs. Required Qualifications 10–15 years of hands-on experience in Physical Design with strong expertise in Static Timing Analysis (STA) . Proven experience in end-to-end timing closure and MCMM timing signoff for block and full-chip designs. Strong expertise in Synopsys PrimeTime (PT/PT-SI) , SDC development , SI/Crosstalk , OCV/AOCV/POCV , CRPR , and ECO timing closure . Solid understanding of the complete Physical Design flow, including Floorplanning, Placement, CTS, Routing, and Signoff . Experience with advanced technology nodes (7nm/5nm/3nm) . Proficiency in Tcl, Perl, or Python scripting for automation. Preferred Qualifications Experience with Fusion Compiler, ICC2, Tempus, StarRC, or RedHawk . Exposure to UPF/Low-Power , hierarchical STA, and advanced packaging technologies. Experience driving timing closure for large-scale, high-frequency CPU, GPU, AI, or Networking SoCs. Why Join Us Work on next-generation AI, HPC, Networking, and Data Center silicon, solving some of the industry's toughest timing closure challenges while influencing the signoff quality of world-class semiconductor products.