FPGA RTL Engineer

FPGA RTL Engineer (FPGA Design, Verification & High-Speed Interface Development) Experience : 2 15+ Years Location : Gurugram/Bengaluru Key Responsibilities 1. Requirements Understanding & Architecture Definition Customer Requirements & Product Definition Engage with product and systems teams to thoroughly understand design intent before committing to implementation: Study and interpret customer requirements and product definition documents; raise clarifications and track requirement changes Translate system-level requirements into block-level technical constraints: gate count budget, clock frequencies, interface bandwidths, and latency targets Participate in customer-facing or internal technical reviews to align on scope, schedule, and design assumptions Architecture & Detailed Design Specification Define architecture and detailed design specifications based on requirements and evaluated trade-offs: Author micro-architecture documents: block diagrams, state machine descriptions, data path sketches, interface signal definitions, and timing budgets Evaluate architectural trade-offs: soft IP vs. hard IP, VHDL vs. Verilog coding approach, pipeline depth vs. resource utilization, and clock domain strategies Define resource estimates (LUT, FF, BRAM, DSP, SERDES) and present architecture proposals at design review gates Document all design decisions and rationale in the engineering design record for traceability through to production 2. RTL Micro-Architecture & Coding Micro-Architecture & Module Coding Implement synthesizable RTL for assigned modules across a range of design complexity levels: Code production-quality RTL in VHDL and/or Verilog: state machines, data path pipelines, control logic, FIFOs, arbiters, and bus interfaces Implement high-speed serial protocol logic covering PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, Aurora, and AMBA-AXI interconnects Design digital signal processing blocks: FIR/IIR filters, FFT/IFFT pipelines, decimation/interpolation chains, and fixed-point arithmetic units Implement memory interface controllers: DDRx, SRAM, and cache management logic optimized for FPGA memory architecture Code peripheral and control interfaces: UART, I2C, SPI, USB, and interrupt controllers with software-accessible register maps Coding Standards & Design Quality Maintain RTL coding quality and consistency across all assigned design blocks: Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.