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About the role
As a Digital IC Design Senior Principal Engineer with Marvell, you ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You ll be part of a key analog team that makes an outsized impact not only for the organization but also to the technological arc of innovation for future generations of Marvells high-speed wireline and optical products. What You Can Expect Marvell is seeking an Analog/Mixed-Signal Design Engineer to contribute to the development of multi-tens of GHz optical and electrical receiver chips. In this role you will be responsible for: Architecture and circuit design. Design of high-performance analog and mixed-signal circuits for electrical and optical products. Design of various analog circuits including ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers. Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support. What Were Looking For Masters degree in Electrical, Electronics & Communication Engineering, preferably with a specialization in Microelectronics or related fields and 15+ years or PhD in Electrical, Electronics & Communication, preferably with a specialization in Microelectronics or related fields with 12+ years of demonstrated experience in high-speed and low-power design on advanced CMOS technologies, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers. Proven track record of successfully bringing multiple tape-outs to production. Ability to independently assess design trade-offs and select the best one based on business needs and implementation risk. Ability to identify, analyze, and resolve complex design challenges and issues, ensuring robust and reliable circuit performance. Ability to technically coordinate the work of junior employees, providing mentorship and guidance. Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements. Proficiency in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits. In-depth knowledge of CMOS process technology, device physics, and the impact of process variations on circuit performance. Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics. Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test, and Physical Design. Strong communication and teamwork skills. Participate and lead design reviews to ensure design quality and compliance with project requirements. Ownership of complex design blocks and complete analog macros. Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication, and high-speed wireline design in general. Lead and contribute to the design of ADCs, DACs, Regulators, Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA, and TX Drivers. Cooperate with system and architecture team in identifying the optimal circuit solution based on overall cost function Supervise, coach and provide technical direction to more junior engineers Supervise and guide layout activities to ensure design accuracy and performance. Conduct post-silicon testing and validation of analog mixed-signal circuits. Collaborate with cross-functional teams to ensure successful project execution. Prepare and maintain detailed documentation of design processes and results.
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