Senior Staff- IP RTL Design Engineer

. Technical Skills . Strong domain expertise in high speed protocols such as UCIe,HBM,Ethernet,DDR,PCIe,USB (direct UCIe / HBM experience strongly preferred) . Extensive hands on experience with SystemVerilog / Verilog (VHDL a plus) Proven experience with RTL quality and sign off flows including Lint,CDC / RDC (e. g.,SpyGlass or equivalent)