Sr. Principal Design Verification Engineer

What You Can Expect Define and drive improvements in DV processes for efficient and high-quality execution Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan development, execution, debug, coverage closure, and gate-level simulations Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive Subsystem-level DV execution Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities Own and debug simulation failures to identify and resolve root causes Architect and implement simulation testbenches using UVM, C Develop and execute test plans to verify design correctness and performance Collaborate with logic designers for thorough verification coverage What Were Looking For Masters/Bachelor s degree with 18+ years of relevant experience. Lead End-to-End PCIe/CXL Subsystem DV execution and sign-off Experience in leading core technical project deliveries in design verification at Subsystem level. Experience in coding UVM Subsystem/block level testbenches, BFM, scoreboards, monitors, etc. Good knowledge of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as PCIe/CXL Proficient in writing and debugging tests in UVM as well as C. Proficient in using Cadence, Synopsys, Mentor and/or ARM verification tools. Nice to have experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Experience in version control tools like GIT, SVN etc Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U. S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U. S. Department of Commerce and/or the U. S. Department of State. Except for U. S. citizens, lawful permanent residents, or protected individuals as defined by 8 U. S. C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.