Principal ASIC Verification Engineer

As a Principal ASIC Design Verification Engineer, you will play a crucial role in providing technical leadership and strategic direction for IP, Subsystem, and SoC verification. Your responsibilities will include: - Acting as a verification technical leader and architect across IP, Subsystem, and SoC programs. - Defining and owning end-to-end verification strategies, methodologies, and best practices across teams. - Architecting highly reusable, scalable, and modular UVM-based verification environments. - Driving cross-project alignment on verification flows, coverage strategies, and sign-off criteria. - Leading complex debug efforts, root-cause analysis, and final functional sign-off for critical programs. - Championing AI-driven, data-driven, and automation-enabled verification solutions to eliminate bottlenecks. - Establishing advanced regression, coverage analytics, and intelligent failure triage workflows. - Mentoring senior and junior verification engineers to raise the overall technical bar of the organization. - Partnering closely with architecture, design, validation, and product teams to influence design-for-verification decisions. - Acting as a key technical interface with internal leadership and external stakeholders. Qualifications required for this role: - Bachelors or Masters degree in Electronic Engineering or a related field. - 1216 years of deep, hands-on ASIC Design Verification experience. - Demonstrated leadership in IP, Subsystem, and SoC-level verification, preferably in networking or packet-processing domains. - Proven experience architecting complex verification environments used across multiple programs. - Expert-level skills in SystemVerilog, UVM, Verilog, C/C++. - Solid mastery of verification methodologies, including constrained-random, coverage-driven verification, and gate-level verification. As a Principal ASIC Design Verification Engineer, you will play a crucial role in providing technical leadership and strategic direction for IP, Subsystem, and SoC verification. Your responsibilities will include: - Acting as a verification technical leader and architect across IP, Subsystem, and SoC programs. - Defining and owning end-to-end verification strategies, methodologies, and best practices across teams. - Architecting highly reusable, scalable, and modular UVM-based verification environments. - Driving cross-project alignment on verification flows, coverage strategies, and sign-off criteria. - Leading complex debug efforts, root-cause analysis, and final functional sign-off for critical programs. - Championing AI-driven, data-driven, and automation-enabled verification solutions to eliminate bottlenecks. - Establishing advanced regression, coverage analytics, and intelligent failure triage workflows. - Mentoring senior and junior verification engineers to raise the overall technical bar of the organization. - Partnering closely with architecture, design, validation, and product teams to influence design-for-verification decisions. - Acting as a key technical interface with internal leadership and external stakeholders. Qualifications required for this role: - Bachelors or Masters degree in Electronic Engineering or a related field. - 1216 years of deep, hands-on ASIC Design Verification experience. - Demonstrated leadership in IP, Subsystem, and SoC-level verification, preferably in networking or packet-processing domains. - Proven experience architecting complex verification environments used across multiple programs. - Expert-level skills in SystemVerilog, UVM, Verilog, C/C++. - Solid mastery of verification methodologies, including constrained-random, coverage-driven verification, and gate-level verification.