Engineer II Verification

To play the role of Verification engineer at the Block level verification. Develop verification test plans from design specifications. Development of test environments using System Verilog and UVM verification methodologies. Integration with RTL and basic simulation bring-up for the design. Create multiple test cases as per test plan and launch regressions. Generate Code/Functional coverage, analyze coverage results and correlate with the test plan. Working the design team members to identify and quickly resolve problems with the design. Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges. Requirements/Qualifications: Bachelor's/Master's degree in Electrical / Electronic Engineering or equivalent. Domain Expertise: AHB, AXI, USB2, USB3 PCIe Protocols Languages (must): Verilog, system Verilog Methodologies: UVM Good knowledge in AI concepts EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog Experience in developing Test Bench components in both block level and SOC level. Experience in Creating test plan and Writing test sequence. Functional Coverage, Code Coverage Assertions (OVA, SVA, PSL) (Desirable) Good analytical and problem-solving skills Excellent written and verbal communication in English. Good teamwork and the desire to excel in a competitive environment. Travel Time: 0% - 25% Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.