Senior Engineer I - Device Modelling

Bachelor or Master s degree in Electrical or Computer Engineering 4-7 years of experience in developing timing power models (NLDM, CCS, etc.) for standard cell, I/O and custom circuits preferably in 12nm and below nodes Hands on experience with running PrimeTime, extracting timing data for custom PnR blocks In depth knowledge of electrical engineering fundamentals including CMOS device operation and characteristics, including understanding of advancing modeling techniques Hands on experience with simulation using HSPICE, Hsim or Finesim Experience with scripting tools such as Python/Perl/Shell etc. Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence) Commitment (responsible, responsive, committed to winning) Work quality ("do it right the first time," attention to detail, good documentation) Strong analytical, problem-solving skills and excellent communication skills Requirements/Qualifications: Exposure to Physical verification using LVS and LPE tools (Synopsys Hercules or Mentor Graphics Calibre and StarRC-XT) Exposure to Static Timing analysis at gate level or transistor level with tools such as PrimeTime or NanoTime Exposure to Standard cell characterization tools such as SiliconSmart Working knowledge of SOC and/or FPGA Architectures Knowledge of FPGA design synthesis and routing associated with Microchip (Libero), Xilinx (ISE), or Altera (Quartus) tools Working knowledge of ASIC/FPGA design flows with a focus on timing and power analysis tools