Senior Memory Controller RTL Design Engineer

Define and implement the micro-architectural specification in Verilog or System Verilog. Refine your implementation for area, power and performance. Integration of the functional IP into SoC. Exercise the functionality of the block by writing basic tests. Perform design quality checks such as Lint, CDC/RDC, Low Power Intent, timing QoR. Automate tasks using scripting and AI for efficiency. Collaborate with IP providers. Deliver high quality functional blocks on schedule and with professional integrity. Challenge the status quo with your growth mindset. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 6 or more years designing and implementing novel high-performance DDR4 or DDR5 memory controllers Background and understanding of Digital Design principles as part of SoC and/or IP development teams Applied understanding of low power design princiles Highly Proficient in Verilog/System Verilog coding constructs. Highly Proficient in high-speed design principles Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Familiarity with Synthesis and STA tools Ability to write scripts using Perl, Tcl, Python etc. Experience with multi-bit error correction such as Reed-Solomon Encoding Understanding of Industry standard interface protocols such as CHI, APB, AMBA