Memory Layout Design Engineer

About the job: Job Role: Memory Layout Design Engineer (2 10 years exp.) Role: Execute Layout Design of SRAM/CAM/RF compiler memories 3nm and lower technology. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories. Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Behavioral Traits: Ability to follow established procedures and work in a distributed team environment. Work independently to deliver high quality results on time. Who can apply: Only those candidates can apply who: have minimum 2 years of experience are Electronics Engineering students Salary: Competitive salary Experience: 2 year(s) Deadline: 2035-01-01 00:00:00